1. Field of the Invention
This invention relates generally to integrated semiconductor circuits and, more particularly, to dynamic random access semiconductor memories. In the read-modify-write operation of a memory unit, a group of data signals is retrieved (or read) from the storage cells of the memory, transferred to a central processing unit for modification, and stored (written) in the same group of storage cells from which they were retrieved.
2. Description of the Related Art
The read-modified-write operation is a time critical operation, particularly in a data processing system in which the operation of the memory unit is synchronized with the operation of the central processing unit. In addition, when the memory unit is operating in a "page" mode, i.e., wherein groups of data signals are retrieved from storage cells in consecutive clock cycles, the timing margins for the operation are even smaller.
Referring to FIG. 1 and FIG. 2, the apparatus and timing diagram for a read operation is shown. The memory unit 10 has address signals, control signals, and a (synchronous) clock (SCLK) signal applied thereto. A group of address and control signals from the central processing unit 5 are applied to the control unit 19 of the memory unit 10. In response, a group of storage cells in the data bit storage array 11 are addressed and the signals retrieved, in response to a read activation control signal, from the storage cells are applied to a data out terminal of the memory unit 10 and to the a parity bit generating unit. Simultaneously with the retrieval of the data bits, a parity signal is retrieved from the parity bit storage unit 12 and applied to the parity bit generating unit 13. In the parity bit generating unit 13, the data bit generated by unit 11 is compared with the retrieved parity signal to determine whether and error has been introduced in the stored data signals. The retrieved data signals are then transferred to the central processing unit along with a parity signal indicating whether the retrieved data is valid. Referring to FIG. 2, the timing diagram showing the relation of the retrieved data signals relative to the SCLK signal, the SCLK signal being the signal which initiates the read cycle. FIG. 2 illustrates that valid data is not available until the middle of the read cycle, the delay being the result of the accessing of the signal storage locations and the associated circuit operation.
Referring to FIG. 3 and FIG. 4, a apparatus and a timing diagram of the typical write operation is summarized. The data in, control signals, and address signals from the central processing unit are applied to the memory unit 10. Within the memory unit 10, the address and control signals from the central processing unit 5 are applied to the control unit 19. Control unit 19 processes these signals distributes the resulting address and control signals in an appropriate manner throughout the memory unit 5. The data in signals are applied to the data bit storage unit 11, in response to a write activation, for storage therein and are applied to the parity generating unit 13. The parity bit resulting from the operation of the parity bit generating unit 13 is stored in the parity bit storage unit 12 at a location related to the associated data bit group. Referring to FIG. 4, the timing relationship of the write cycle relative to the SCLK signal is shown. Of particular interest is that valid data must be available prior to the initiation of the write cycle in order that the parity bit can be stored simultaneously with the data bits.
Referring to FIG. 5, the timing of the data transfer relative to the SCLK signal is shown for the read-modify-write operation. During the first clock cycle, the data is retrieved from the memory unit 10 and transferred to the central processing unit 5 shown in FIG. 1. The central processing unit 5 modifies the data group and transfers the modified data group to the memory unit 10 before starting the third clock cycle, i.e., the write operation cycle for the memory unit 10. The transfer is the result of the requirement that the input data preparation (data set-up) occur before starting the write operation. The memory unit 10 stores the modified data group at the same address from which the data group was retrieved from the central processing unit 5 during the third clock cycle. However, the parity checking operation of a read operation can not begin until the valid data is retrieved from the data bit storage unit. And during the write operation, the parity generation must begin as soon as possible because the generated parity bit and the data group applied to the memory unit must be stored simultaneously. Therefore, the read-modify-write operation can be a time critical operation in which the to avoid conflict in the memory unit 10.
A need has therefor been felt for apparatus and an associated technique for reducing the possible conflict in the memory unit during a read-modify-write operation.